quartus常见警告.docVIP

1、Warning (10227): Verilog HDL Port Declaration warning at PRESS_MODELE.v(29): data type declaration for iR declares packed dimensions but the port declaration declaration does not. 解释： 2、Warning: PLL DE2_TV:inst1|Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|pll output port clk[0] feeds output pin DRAM1_CLK via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance 解释：PLL的输出用在了非专属的PLL_OUT 措施：设计电路板的时候最好将PLL_OUT用在相关的时钟信号上，如果没有使用，则这个警告不理会也可。 3、Warning: Using design file cpu