基于verilog的fsk调制与解调(呕心沥血,极度精简).doc

先上程序（verilog语言编写） `timescale 1ns/1ns // 测试程序 module test; reg clk1,rst1,clk2,rst2; reg din1; wire dout1,ddout1; modulator my1(.clk(clk1),.rst(rst1),.din(din1),.dout(dout1)); demodulator my2(.clk(clk2),.rst(rst2),.ddin(dout1),.ddout(ddout1)); initial begin clk1=0; forever #25 clk1=~clk1; end initial begin clk2=0; forever #10 clk2=~clk2; end initial begin rst1=1; #15 rst1=0; #50 rst1=1; end initial begin rst2=1; #5 rst2=0; #25 rst2=1; end initial begin #25 din1=1; #400 din1=1; #400 din