ofanewESDpowerclampcircuit创新.PDFVIP

007 Microelectronics Reliability Microelectronics Reliability 50 (2010) 1087–1093 Characteristics analysis and optimization design of a new ESD power clamp circuit Hongxia Liu *, Baojun Tang, Yue Hao Key Lab of Ministry of Wide Band-Gap Semiconductor Technology, School of Microelectronics, Xidian University, Xi’an 710071, China a r t i c l e i n f o a b s t r a c t Article history: As CMOS technology scales down, the design of ESD protection circuits becomes more challenging. Received 28 October 2009 There are some disadvantages for the actual power clamp circuit. In this paper, an optimization ESD Received in revised form 10 April 2010 power clamp circuit is proposed. The new clamp circuit adopts the edge triggering True Single Phase Clocked Logic (TSPCL) D flip-flop to turn on and time delay, it has the advantage of dynamic transmis- sion structure. By adding a leakage transistor of small size, the clamp circuit can turn off effectively. By changing the W/L ratio, the clamp can safely protect the gate of ESD power clamp devices from ther- moelectric breakdown. The results show that the circuit can reduce the false triggering and power supply noise more effectively, it can be widely used in high-speed integrated circuits. The