第十三章数模混合IP.pptVIP

第十三章 数模混合IP的设计与集成 Outlines Agenda Why need mixed-signal design? Some function cannot be implemented by ONLY digital principle!!! The conventional mixed-signal design operation Digital part included in VLSI chips, analog part outside, connected with each other by IO pad Example: USB PHY Advantages: Easy design for chip Reduce the single chip size Limits: Enlarge the system size, not chip size More bad effect from parasitic in PCB between two parts More difficulties in the consideration on IO pads, driving and load Mixed-signal design for SoC Digital and analog parts integrated in ONE chip Benefits: Reduce the system size Reduce the consideration on parasitic on PCB Reduce the IO driving currents and parasitic loads Limits: May enlarge the chip size Increase process complexity Noise isolation carefully The mixed-signal design or IP in SoC The normal design or IP PLL ADC The parts’ respective function Digital: Controlling logic and simple algorithm Analog: Communicating with external analog signal and dealing with the voltage outside the digital value margin Agenda ADC General Usage To convert the analog voltage or current value into digital codes For battery power capacitance detection For key-board press detection Etc. Conventional Mixed Signal Design Approach How SA ADC Function? Compare MSB first, then down to LSB Example: 3-bit Successive approximation Key Algorithm Implementation Newton Division R-2R network SA ADC Specification Successive approximation algorithm 6 bits converter data output Two analog input selection Low power with power down switch Internal reference voltage generator The flags of start of conversion and end of conversion The General Structure of SAR ADC ADC Digital Part Design Sub-module Definition, using Verilog RTL to implement Control Logic Synchronize the input signal Send the soc flag to all module Generate the eoc flag and collect the converter data output to the system Pat Generator According to the soc flag to generate converter