an951在pcie背板上驱动长线以简化评估-AN951DrivingLong.PDFVIP

AN951: Driving Long Traces on PCIe Backplanes for Simple Evaluation It is becoming common in server and storage applications to require more than twenty 100 MHz PCIe Gen 2/3 clock outputs for various system functions and ICs. Along with KEY EVB FEATURES this high fan-out count, designing clock traces longer than ten inches and hybrid models driving high speed cables over HSMC connectors in addition to long traces are becom- • Two types of traces: ing increasingly common. In these design cases, designers are always concerned about • Traces on the top layer of a 6-layer PCB. jitter margin and performance, receiver signal integrity requirements that the driver • Traces in the middle layer (layer 3) of a needs to satisfy, and the impact of aggressor signals on PCIe jitter performance. 6-layer PCB. • 100 Ω differential impedance trace This application note analyzes different real world PCIe circuit designs and how different (Z = 50 Ω). 0 trace lengths, trace impedance, and aggressors will impact signal integrity and jitter per- • 85 Ω differential impedance trace formance. The analysis is done using evaluation boards designed to closely replicate (Z = 42.5 Ω). 0 the different scenarios of the circuit design mentioned above. • An aggressor signal along with the PCIe