TP RAM的低功耗设计和应用.pdf

Open Journal of Circuits and Systems 电路与系统, 2017, 6(1), 1-7 Published Online March 2017 in Hans. /journal/ojcs /10.12677/ojcs.2017.61001 Low Power Design of TP RAM and Its Application Qingjun Zhou, Jing Xing ZTE Telecom College, Xian Peihua University, Xi’an Shaanxi th st st Received: Mar. 8 , 2017; accepted: Mar. 21 , 2017; published: Mar. 31 , 2017 Abstract As the area and power consumption of TP RAM in SoC are large, a new design method of optimiza- tion is proposed. In order to achieve the function of the original TP RAM and keep the external in- terface unchanged, TP RAM is replaced with SP RAM, and read-write interface logics of conversion are added around SP RAM. The method discussed in this paper is used in the multi core SoC chip which has been successfully taped out in TSMC 28 nm HPM process. The chip occupies 10.7 mm × 11.9 mm of die area and consumes 19.8 W. The testing results indicate that the area of optimized RAM is reduced by 24.5%, and the power saving is 45.16%. Keywords TP RAM, SP RAM, Optimization of Power Consumption, Interface Logics of Conversion TP RAM的低功耗设计及应用 周清军，邢 静 西安培华学院中兴电信学院，陕西 西安 收稿日期：2017年3月8 日；录用日期：2017年3月21 日；发布日期：2017年3月31 日 摘 要 针对SoC 中TP RAM的面积及功耗较大问题，提出一种优化设计方法。通过将SoC 中的TP RAM替换成SP RAM，并在SP RAM外围增加读写接口转换逻辑，使替换后的RAM实现原TP RAM 的功能，保持对外接口 不变。将文中方法应用于一款多核SoC芯片，该芯片经TSMC 28 nm HPM工艺成功流片，die size为10.7 mm × 11.9 mm，功耗为19.8 W 。测试结果表明：优化后的RAM面积减少了24.5%，功耗降低了45.16% 。 文章引用: 周清军, 邢静. TP RAM 的低功耗设计及应用[J]. 电路与系统, 2017, 6(1): 1-7. /10.12677/ojcs.2017.61001 周清军，邢静 关键词 TP RAM，SP RAM，功耗优化，接口转换逻辑 Copyright © 2017 by authors and Hans Publishers Inc. This work is licensed under the Creative Commons Attribution International License (CC BY). /lic