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?未经作者允许，请勿发布该文档！yingqichen@ VHDL Simulation Synthesis 基本逻辑电路设计 门电路 与非门，或非门，反相器，多输入与门 编码器，译码器，多路选择器 运算器 加法器，加减法器，乘法器，求补器 存储器 ROM，RAM，FIFO 时序逻辑电路设计 触发器 D，T， JK 寄存器 8b通用寄存器，循环移位寄存器， 计数器 同步，可逆，具有数据加载，进位控制，清零，置位功能的计数器，异步计数器 condsig.vhd Library IEEE ;use IEEE.std_logic_1164.all ; ENTITY condsig IS PORT ( input0, input1, sel : IN BIT; output : OUT BIT);END condsig; ARCHITECTURE maxpld OF condsig ISBEGIN output = input0 WHEN sel = 0 ELSE input1;END maxpld; Reg12.vhd Library IEEE ;use IEEE.std_logic_1164.all ; ENTITY reg12 IS PORT( d : IN BIT_VECTOR(11 DOWNTO 0); clk : IN BIT; q : OUT BIT_VECTOR(11 DOWNTO 0)); END reg12; ARCHITECTURE a OF reg12 IS BEGIN PROCESS BEGIN WAIT UNTIL clk = 1; q = d; END PROCESS; END a; Comparator8.vhd library IEEE; use IEEE.Std_logic_1164.all; entity HCT688 is port(Q, P : in std_logic_vector(7 downto 0); GBAR : in std_logic; PEQ : out std_logic); end HCT688; architecture VER1 of HCT688 is begin PEQ = 0 when ((To_X01(P) = To_X01(Q)) and (GBAR = 0)) else 1; end VER1; Comparator8.vhd (1) Latchinf.vhd Library IEEE ; use IEEE.std_logic_1164.all ; ENTITY latchinf IS PORT ( enable, data : IN BIT; q : OUT BIT); END latchinf; ARCHITECTURE maxpld OF latchinf IS BEGIN latch : PROCESS (enable, data) BEGIN IF (enable = 1) THEN q = data; END IF; END PROCESS latch; END maxpld; conversion_altera.vhd LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY adder IS PORT (op1, op2 : IN UNSIGNED(7 downto 0); result : OUT INTEGER); END adder; ARCHITECTURE maxpld OF adder IS BEGIN result = CONV_INTEGER(op1 + op2); END maxpld; condsigm.vhd Library IEEE ; use IEEE.std_logic_1164.all ; ENTITY condsigm IS PORT ( high, mid, low : IN BIT; q : OUT INTEGER); END condsigm; ARCHITECTURE maxpld OF condsigm IS BEGIN q = 3 WHEN high = 1 ELSE -- when high 2 WHEN mid = 1 ELSE -- when mid but not high 1 WHEN low = 1 ELSE -- when low but not mid