PCIE_3.0简介及信号和协议测试方法(国外英语资料).docVIP

PCIE_3.0简介及信号和协议测试方法(国外英语资料) PCIE 3.0 introduction and signal and protocol testing methods Agilent technology (China) co., LTD. : li kai One, foreword PCI Express (PCIE) bus is a serial version of the PCI bus, which is multispeed serial The difference signal is transmitted at high speed, and the signal rate for each pair of difference lines can be 2.5 Gbps and 2 generations 5Gbps and now the three generation 8Gbps that are being used. PCIE standards are developed by the pci-sig organization, and since its introduction, the 1 and 2 standards have been in the PC and The popularity of servers is being used to support high speed graphics CARDS and other requirements for high-speed data transmission. Pci-sig developed PCIE 3.0 in 2010 for the purpose of supporting higher bus data throughput The PCIE 3 code. At the moment, PCIE 3.0 is starting to appear on some high-end servers, and its common The use of PCS is also on the horizon. So what are the features of the PCIE 3.0 bus? What is special about its testing? We this So lets talk about that. PCIE 3.0 The signal rate changes First, lets look at the purpose of the PCIE 3 specification, which is aimed primarily at existing FR4 boards The materials and connectors provide a higher rate of effective data transmission than PCIE 2, while remaining and original There are 1 generation, 2 generation equipment compatible. Its a simple goal, but it wont be easy. We know that PCIE 2s data transfer rate for every difference line is 5Gbps, compared to 1 generation High 1 times; And the third generation is going to double the rate relative to the 2 generations, so its natural to transfer the data Rate of up to 10 GBPS. But this 10Gbps stumped pci-sig because of the PC and Server On the cost side, cheap FR4 PCB and cheap connectors are generally used, no matter what It is difficult to make sure that the 10Gbps signal can be transmitted reliably on the original signal path Distance (typical distance is 15 ~ 30cm). So pci-sig finally decid