编写的全数字锁相环的代码.docVIP

全数字锁相环的verilog源代码,仿真已通过 module dpll(reset,clk,signal_in,signal_out,syn); parameter para_K=4; parameter para_N=16; input reset; input clk; input signal_in; output signal_out; output syn; reg signal_out; reg dpout; reg delclk; reg addclk; reg add_del_clkout; reg [7:0]up_down_cnt; reg [2:0]cnt8; reg [8:0]cnt_N; reg syn; reg dpout_delay; reg [8:0]cnt_dpout_high; reg [8:0]cnt_dpout_low; /******phase detector*****/ always@(signal_in or signal_out) begin dpout=signal_in^signal_out; end /******synchronization establish detector*****/ always@(posedge clk or negedge reset) begin if(!reset) dpout_delay=b0; else dpout_delay=dpout; end always@(posedge clk or negedge reset) begin if(!reset) begin cnt_dpout_high=b0; cnt_dpout_low=b0; end else if(dpout) if(dpout_delay==0) cnt_dpout_high=b0; else if(cnt_dpout_high==8 cnt_dpout_high=b0; else cnt_dpout_high=cnt_dpout_high+1; else if(!dpout) if(dpout_delay==1) cnt_dpout_low=b0; else if(cnt_dpout_low==8 cnt_dpout_low=b0; else cnt_dpout_low=cnt_dpout_low+1; end always@(posedge clk or negedge reset) begin if(!reset) syn=b0; else if((dpout!dpout_delay)||(!dpoutdpout_delay)) if(cnt_dpout_high[8:0]-cnt_dpout_low[8:0]=4||cnt_dpout_low[8:0]-cnt_dpout_high[8:0]=4) syn=b1; else syn=b0; end /****up down couter with mod=K****/ always@(posedge clk or negedge reset) begin if(!reset) begin delclk=b0; addclk=b0; up_down_cnt= end else begin if(!dpout) begin delclk=b0; if(up_down_cnt==para_K-1) begin up_down_cnt= addclk=b0; end else begin up_down_cnt=up_down_cnt+1; addclk=b0;