2011年《数字系统设计》试卷A部分答案.pptx

4．按要求转换下列程序。 （1） WAIT UNTIL clock’EVENT AND clock=‘1’; q = data; （2）If a(3)=1 then Y=”11”; Elsif a(2)=1 then Y=”10”;Elsif a(1)=1 then Y=”01”; Else Y= 00 ;End if; ;三、电路设计题 （43分） 1．解答：参考 library ieee; use ieee.std_logic_1164.all; entity singen_tb is end singen_tb; architecture TB_ARCHITECTURE of singen_tb is component sin_gen port( clk : in std_logic; rst : in std_logic; q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); end component; signal clk : std_logic; signal rst : std_logic; signal qout : STD_LOGIC_VECTOR(7 DOWNTO 0); begin UUT : sin_gen port map ( clk = clk, rst = rst, q = qout ); STIMULUS: process begin rst = 0; wait for 100 ns; --0 fs rst = 1; wait for 1 us; wait; end process; CLOCK_ : process begin clk = 0; wait for 50 ns; --0 fs clk = 1; wait for 50 ns; --50 ns end process; end TB_ARCHITECTURE;;;Answer whether each of the VHDL code has the same behaviour as the timing diagram Notes: 1)”same behaviour” means that the signals a,b,and c have the same values at the end of each clock cycle in steady-state simulation(ignore any irregularities in the first few clock cycles) 2)for full marks, if the code does not match, you must explain why. 3) assume that all signals, constrants, variables, types, etc are properly defined and declared. 4) all of the codes are leagal, synthesizable VHDL code.;Answer whether each of the VHDL code has the same behaviour as the timing diagram Notes: 1)”same behaviour” means that the signals a,b,and c have the same values at the end of each clock cycle in steady-state simulation(ignore any irregularities in the first few clock cycles) 2)for full marks, if the code does not match, you must explain why. 3) assume that all signals, constrants, variables, types, etc are properly defined and declared. 4) all of the codes are leagal, synthesizable VHDL code.;C DIFFERENT: The signal a is assigned the value of c from the previous clock cycle. This value is NOT b which is a from two cycles ago. The sig