LDO工作原理详解剖析.pptVIP

* * Dropout voltage is the minimum input to output voltage differential required for the regulator to sustain an output voltage within 100mV of its nominal value. Use of an NPN power transistor requires more than 1V of drop-out mainly due to the need to provide at least 0.6V to forward bias a base emitter junction. LDO (Low Drop-Out) regulators on the other hand use a PNP for the power transistor. This PNP is allowed to saturate and thereby requires much less drop-out voltage. Newer developments using a CMOS power transistor can provide the lowest drop-out voltage. With CMOS the only voltage d