LDO工作原理详解剖析.ppt

* * Dropout voltage is the minimum input to output voltage differential required for the regulator to sustain an output voltage within 100mV of its nominal value. Use of an NPN power transistor requires more than 1V of drop-out mainly due to the need to provide at least 0.6V to forward bias a base emitter junction. LDO (Low Drop-Out) regulators on the other hand use a PNP for the power transistor. This PNP is allowed to saturate and thereby requires much less drop-out voltage. Newer developments using a CMOS power transistor can provide the lowest drop-out voltage. With CMOS the only voltage drop across the regulator is the ON resistance of the power device times the load current. With very light loads this can become just a few tens of millivolts. The Quasi-LDO fits between the standard NPN regulator and the PNP-based low-dropout (LDO) regulator, in terms of regulation performance and dropout voltage. The key difference between the three types of regulator is the pass transistor configuration. The NPN regulator uses an NPN-Darlington driven by a PNP as its pass device. This requires very little drive current from the error amplifier to handle a large load current, but it constrains the minimum voltage drop from input to output. The PNP-based LDO has a simpler pass device, consisting of one PNP driven by a second lower-current PNP. The dropout voltage is only one VBE, about 0.6V. However, a much higher operating current is needed in proportion to the load. A quasi-LDO regulator uses an NPN as the main pass transistor, driven by a PNP. As the NPN usually has more current gain than does a PNP, this gives the regulator more gain compared to the traditional LDO, and therefore better load regulation - but not as good as the standard NPN regulator. But with only one NPN instead of a Darlington in the pass device, the quasi-LDO has a lower dropout, a VCE(sat) plus a VBE, or about 1V. Operating current for the quasi-LDO will be lower than for an LDO, but generall