The Stanford DASH multiprocessor：（斯坦福冲多处理器）.pdfVIP

The Stanford Dash Multiprocessor Daniel Lenoski, JamesLaudon, Kourosh Gharachorloo, Wolf-Dietrich Weber, Anoop Gupta, John Hennessy, Mark Horowitz, and Monica S. Lam Stanford University he Computer Systems Laboratory at Stanford University is developing a shared-memory multiprocessor called Dash (an abbreviation for Direc- tory Architecture for Shared Memory). The fundamental premise behind the architecture is that it is possible to build a scalable high-performance machine with a single address space and coherent caches. The Dash architecture is scalable in that it achieves linear or near-linear performance growth as the number of processors increases from a few to a few thousand. This performance results from distributing the memory among process- ing nodes and using a network with scalable bandwidth to connect the nodes. The architecture allows shared data to be cached, thereby significantly reducing the latency of memory accesses and yielding higher processor utilization and higher Directory-based overall performance. A distributed directory-based protocol provides cache co- cache coherence gives herence without compromising scalability. The Dash prototype system is the first operational machine to include a scalable Dash the ease-of-use cache-c