(数字电子技术）CH45触发器的VHDL语言描述及仿真.pdf

4.5 触发器的VHDL描述及其仿真 4.5 [例4.5.1] 同步D触发器的VHDL描述和仿真 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY d_ff is PORT (d,clk,reset : INSTD_LOGIC; q : OUTSTD_LOGIC); END d_ff; ARCHITECTURE one OF d_ff IS BEGIN PROCESS (clk) BEGIN IF clkEVENT AND clk=1 THEN IF reset=1 THEN Q=0; ELSE q=d; END IF; END IF; END PROCESS;