MT46H32M32LFJG-6A;MT46H32M32LFJG-6A TR;MT46H32M32LFJG-5 ITA;中文规格书,Datasheet资料.pdfVIP

Preliminary‡ 168-Ball x16, x32 Mobile LPDDR PoP (TI OMAP)Mobile DDR SDRAM Addendum Mobile LPDDR 168-Ball Package-on-Package (PoP) TI OMAP™ MT46HxxxMxxLxJG Features Options Marking • Vdd/Vddq = 1.70–1.95V • Vdd/Vddq • Bidirectional data strobe per byte of data (DQS) – 1.8V/1.8V H • Internal, pipelined double data rate (DDR) • Configuration architecture; 2 data accesses per clock cycle – 128 Meg x 16 (32 Meg x 16 x 4 128M16 • Differential clock inputs (CK and CK#) banks) • Commands entered on each positive CK edge – 64 Meg x 32 (16 Meg x 32 x 4 banks) 64M32 • DQS edge-aligned with data for READs; center- – 64 Meg x 16 (16 Meg x 16 x 4 banks) 64M16 aligned with data for WRITEs – 32 Meg x 32 (8 Meg x 32 x 4 banks) 32M32 • 4 internal banks for concurrent operation • Device version • Data masks (DM) for masking write data—one mask – Single die, standard addressing LF per byte – 2-die stack, standard addressing L2 • Programmable burst lengths (BL): 2, 4, 8, or 161 • Plastic “green” package • Concurrent auto precharge option is supported