64位超前进位对数加法器的设计与优化_王仁平.pdfVIP

Design and Development of IC doi: 1013969/j1issn11003- 353x120101111017 64 王仁平, 何明华, 陈传东, 戴惠明, 黄扬国 ( 福州大学 物理与信息工程学院, 福州350108) : 设计 一个应用于高性能微处理器的快速64 位超前进位对数加法器通过分析超前进 位对数加法器原理, 提 了改进四进制Kogge-Stone 树算法的64 位超前进位对数加法器结构, 并 结合使用多米诺动态逻辑时钟延迟多米诺逻辑和传输门逻辑等技术来设计和优化电路该加法 器采用SMIC 0118 Lm CM S 工艺实现, 在最坏情况下完成一次加法运算时间为48611ps, 与相同 工艺和相同电路结构采用静态CM S 实现相比, 大大减少了加法器各级门的延迟时间, 取得良好 的电路性能 : 多米诺动态逻辑; 时钟延时多米诺; 对数加法器; 点操作; Kogge-Stone树 : TN432 : A : 1003- 353X (2010) 11- 1116- 06 Design and Optimization of 64-Bit Look-Ahead Logarithmic Adders Wang Renping, He Minghua, Chen Chuandong, Dai Huiming, Huang Yangguo ( College of Physics and Inf ormation Engineering, Fuzhou University, Fuzhou 350108, China) Abstract: A fast 64-bit look-ahead logarithmic adder applying to high-performance microprocessors was designed1 By analyzing the look-ahead adder, the 64-bit look-ahead logarithmic adder structurewas proposed, which based on the improved radix-4 Kogge-Stone tree algorithm, and combined the domino dynamic logic, clock-delay domino logic and transmission gateto design and optimizethe circuit1 Using SMIC 0118Lm CM S process, in theworst case, the computation time is 48611 ps, which greatly reduces all levels of thegate delay time and makes a good performance compared with that of the circuit based on the static CM S with the same process and circuit structure1 Key words: domino dynamic logic; clock-delay domino; logarithmic adder; dot operations; Kogge- Stone tree EEACC: 2570D [1- 3] 1632 0 引言 , 64 (ALU) , GHz, , , , [4- 6] , , , 64 ,