集成电路版图设计基础第三篇：数字IC版图.pptVIP

school of phye basics of ic layout design * Clock Tree Optimization (CTO)： what are the different CTO options and how do they reduce skew? skew: 就是从时钟树根(clock root)到所有的寄存器之中,最长和最短的插入延迟的相差。就是: clk1_skew = clk1_max_insertion_delay - clk1_min_insertion_delay the different options in CTO to reduce skew are described in the following list. 1 Buffer and Gate Sizing 2 Buffer and Gate Relocation 3 Level Adjustment 4 Reconfiguration 5 Delay Insertion 6 Dummy Load Insertion 版图设计过程 - CTO school of phye basics of ic layo