第4章VHDL设计实例.pptVIP

第四章;组合逻辑电路设计 时序逻辑电路设计 存储器设计 状态机设计;一、4选1多路选择器 ;LIBRARY IEEE; USE IEEE.std_logic_1164.all; ENTITY mux4 IS PORT (a,b,c,d,s0,s1: IN std_logic; y: OUT std_logic ); END mux4; ARCHITECTURE func OF mux4 IS VARIABLE sel:std_logic_vector(1 DOWNTO 0)； BEGIN sel=s1s0; y = a WHEN sel =‘00 ELSE b WHEN sel =‘01’ ELSE c WHEN sel =‘10’ ELSE d WHEN sel =‘11’ ELSE ‘X’; END func; ;;LIBRARY IEEE; USE IEEE.std_logic_1164.all; ENTITY encoder8_3 IS PORT (d: IN std_logic_vector(7 downto 0); y0,y1,y2: OUT std_logic ); END encoder8_3; ARCHITECTURE func OF encoder8_3