第二三章Verilog语法的基本概念及常用Verilog语法之一教程.ppt

Wire：wire型数据的确认符；n-1:0表示数据的位宽，即该数据有几位；最后是数据的名字（变量的名字）。 如果一次定义多个数据，数据名之间用逗号隔开，最后用分号表示语句结束。 若没有说明位宽，则位宽为1bit。 When a signal is driven by a module output, a primitive output, or a continuous assignment. Use a net type A net data type must be used when a signal is . Driven by the output of a module instance or primitive instance . Connected to an input or inout port of the module in which it is declared. . On the left-hand side of a continuous assignment. 默认为unsigned，除非明确说明为singned 若没有说明位宽，则位宽为1bit。 Variable data types are used as temporary storage of programming data. * * Reg[n-1:0]定义了存储器中每个存储单元的大小；存储器名后的[m-1:0]则定义了该存储器中有多少个这样的寄存器，最后用分号结束。 对存储器进行地址索引的表达式必须是常数表达式 Reg[n-1:0]定义了存储器中每个存储单元的大小；存储器名后的[m-1:0]则定义了该存储器中有多少个这样的寄存器，最后用分号结束。 对存储器进行地址索引的表达式必须是常数表达式 Reg[n-1:0]定义了存储器中每个存储单元的大小；存储器名后的[m-1:0]则定义了该存储器中有多少个这样的寄存器，最后用分号结束。 对存储器进行地址索引的表达式必须是常数表达式 Verilog的运算符范围很广 * * %， 取模，求余数 * Reg;默认为无符号数，除非声明为signed。 As a general rule, all operands in an expression are first expanded to the size of the largest vector in the statement (including both sizes of an assignment statement). Concatenate and replicate operations are evaluated before the expansion, and represent a new vector size. Unsigned operands are expanded by left-extending with zero. Signed operands are expanded by left-extending with the value of the most-significant bit (the sign bit)。 * Reg;默认为无符号数，除非声明为signed。 As a general rule, all operands in an expression are first expanded to the size of the largest vector in the statement (including both sizes of an assignment statement). Concatenate and replicate operations are evaluated before the expansion, and represent a new vector size. Unsigned operands are expanded by left-extending with zero. Signed operands are expanded by left-extending with the value of the most-significant bit (the sign bit)。 * * * * * * 行为级描述， 两个always并行执行 * * 下面先介绍几个简单的Verilog HDL程序,然后从中分析Verilog HDL程序的特性。 这个例子描述了一个三位的加法器。从例子中可以看出整个Verilog HDL程序是嵌套在module和endmodule声明语句里的。 * 这个程序描述了一个比较器. 注释只是