第5讲-用verilog语言建模组合逻辑.ppt

* * 2.1 并行编码器 `timescale 1ns/100ps module parallel_encode(int1,int2,int3,int4,vector,valid); input int1,int2,int3,int4; output [0:1] vector; output valid; reg [0:1] vector; assign valid = int1 | int2 | int3 | int4; always @(int1 or int2 or int3 or int4) begin case({int1,int2,int3,int4}) 4b1000: vector = 2b00; 4b0100: vector = 2b01; 4b0010: vector = 2b10; 4b0001: vector = 2b11; default:vector = 2b00; endcase end endmodule Case实现并行结构 * * 2.2 优先级编码器 `timescale 1ns/100ps module parallel_encode(int1,int2,int3,int4,vector,valid); input int1,int