第5讲-用verilog语言建模组合逻辑.ppt

* * 2.1 并行编码器 `timescale 1ns/100ps module parallel_encode(int1,int2,int3,int4,vector,valid); input int1,int2,int3,int4; output [0:1] vector; output valid; reg [0:1] vector; assign valid = int1 | int2 | int3 | int4; always @(int1 or int2 or int3 or int4) begin case({int1,int2,int3,int4}) 4b1000: vector = 2b00; 4b0100: vector = 2b01; 4b0010: vector = 2b10; 4b0001: vector = 2b11; default:vector = 2b00; endcase end endmodule Case实现并行结构 * * 2.2 优先级编码器 `timescale 1ns/100ps module parallel_encode(int1,int2,int3,int4,vector,valid); input int1,int2,int3,int4; output [0:1] vector; output valid; reg [0:1] vector; assign valid = int1 | int2 | int3 | int4; always @(int1 or int2 or int3 or int4) begin if(int1) vector = 2b00; else if(int2) vector = 2b01; else if(int3) vector = 2b10; else if(int4) vector = 2b11; else vector = 2b00; end endmodule If 优先级结构 * * 三 译码器 完成对信号的译码，分解信号的意义 处理器的指令译码器 使用case语句完成编码 `timescale 1ns/100ps module decode3_8 (data_in ,en ,data_out ); input [2:0] data_in ; input en ; output [7:0] data_out ; reg [7:0] data_out ; always @(data_in or en ) begin data_out = {8{1b0}}; if (en == 1) begin case (data_in [2:0]) 3b000 : data_out [7:0] = 8 3b001 : data_out [7:0] = 8 3b010 : data_out [7:0] = 8 3‘b011 : data_out [7:0] = 8’ 3b100 : data_out [7:0] = 8 3b101 : data_out [7:0] = 8 3b110 : data_out [7:0] = 8 3b111 : data_out [7:0] = 8 default : data_out [7:0] = {8{1b0}}; endcase end end endmodule * * 三 数据选择器 简单的选择器由条件表达式完成 复杂的选择器由行为级建模语句完成 `timescale 1ns/100ps module mux_8(addr,in1, in2, in3, in4, in5, in6, in7, in8,mout,ncs); input [2:0] addr; input [7:0]in1, in2, in3, in4, in5, in6, in7, in8; input ncs; output [7:0] mout; reg [7:0] mout; always@(addr or i