电路设计专题概要1.pptxVIP

电路设计专题; Design Entry Schematic capture Hardware Description Languages Logic Synthesis Pre layout verification Functional simulation Formal methods Timing Analysis Floorplanning Placement Routing Extraction Post layout verification;CLBs Composed of: LUTs (lookup tables): perform combinational logic Flip-flops: perform sequential functions Multiplexers: connect LUTs and flip-flops ;Composed of: CLBs (Configurable logic blocks): perform logic IOBs (Input/output buffers): interface with outside world Programmable interconnection: connect CLBs and IOBs Some FPGAs include ot