VerilogHDL简易时钟层次化设计程序代码.doc

VerilogHDL简易时钟的层次化设计程序代码 module top(clk0,clk1,q,s); input clk1,clk0; output[7:0] q; //reg[7:0] q; output[2:0]s; //reg[2:0]s; wire[23:0] w; cnt60 m0(clk1,w[7:0],cp0); //秒计数模块 cnt60 m1(cp0,w[15:8],cp1); //分计数模块 cnt24 m2(w[23:16],cp1); //时计数模块 wx m3(clk0,clk1,c,s,w[3:0],w[11:8],q,w[19:16],w[6:4],w[14:12],w[21:20]); endmodule module wx(clk0,clk1,c,s,c0,c3,q,c6,c1,c4,c7); input clk0,clk1; input[3:0] c0,c3; input[2:0] c1,c4; input[3:0] c6; input[1:0]c7; output[7:0]q; reg[7:0]q; output [2:0]s; output [3:0]c; reg [3:0]c; reg [2:0]s1,s; //位选 always@(posedge clk0) begin if(s13b111)s1=s1+1b1; else s1=3b000; case(s1) 3b000:begin s=3b000;c=c0;end 3b001:begin s=3b001;c=c1;end 3b011:begin s=3b011;c=c3;end 3b100:begin s=3b100;c=c4;end 3b110:begin s=3b110;c=c6;end 3b111:begin s=3b111;c=c7;end default begin s=3b000;c=c0;end endcase end //always@(posedge clk1) (有误，不要) always@(c) case(c) 4b0000:q=8 4b0001:q=8 4b0010:q=8 4b0011:q=8 4b0100:q=8 4b0101:q=8 4b0110:q=8 4b0111:q=8 4b1000:q=8 4b1001:q=8 default q=8 endcase endmodule //60计数 module cnt60(clk,qs,co); input clk; output [7:0] qs; output co; reg[7:0] qs; reg co; always@(posedge clk) begin if(qs[7:4]!=5) begin if(qs[3:0]==4b1001) begin qs[7:4]=qs[7:4]+1b1;qs[3:0]=4b0000;co=1b0;end else begin qs[7:4]=qs[7:4];qs[3:0]=qs[3:0]+1b1;co=1b0;end end else if(qs[3:0]==4b1001) begin qs[7:4]=4b0000;qs[3:0]=4b0000;co=1b1;end else begin qs[7:4]=qs[7:4];qs[3:0]=qs[3:0]+1b1;co=1b0;end end endmodule // 24计数(无误) module cnt24(qh,clk); input clk; output [7:0] qh; reg[7:0] qh; always@(posedge clk) begin if(qh[7:4]!=2) begin