东北大学EDA数字系统设计第三章改.ppt

第3章 典型Verilog HDL设计实例;3.1 组合逻辑电路设计;;3.1.1逻辑门电路设计;例3-1用Verilog HDL设计实现如下逻辑表达式所对应的基本逻辑门电路 ;module example3_1 (a,b,c,d,e,f,g, f1,f2,f3,f4,f5,f6,f7); input a,b,c,d,e,f,g; output f1,f2,f3,f4,f5,f6,f7; assign f1 = ~ a; assign f2 = b c; assign f3 = ~(b c); assign f4 = d | e; assign f5 = ~(d | e); assign f6 = f ^ g; assign f7 = f ~^ g; endmodule ;module example3_1 (a,b,c,d,e,f,g, f1,f2,f3,f4,f5,f6,f7); input a,b,c,d,e,f,g; output f1,f2,f3,f4,f5,f6,f7; assign f1 = ~ a; assign f2 = b c; assign f3 = ~(b c); assign f4 = d | e; assign f5 = ~(d | e); assign f6 = f ^ g; assign f7 = f ~^ g; endmodule;例3-2 用Verilog HDL设计实现如下逻辑表达式所对应的逻辑门电路 ;module example3_2 (a,b,c,d,f); input a,b,c,d; output [3:0] f;? assign f[0] = (a b) | (b c) | (~ b ~ c); assign f[1] = (a b c) | ~(~ a | ~ b | c); assign f[2] = (a ^ b ^ c) | (~(d) (a | c)); assign f[3] = ~((a b) ^ (c d)) | ((a b d) ^ (b c d)); endmodule;module example3_2 (a,b,c,d,f); input a,b,c,d; output[3:0] f;? assign f[0] = (a b) | (b c) | (~ b ~ c); assign f[1] = (a b c) | ~(~ a | ~ b | c); assign f[2] = (a ^ b ^ c) | (~(d) (a | c)); assign f[3] = ~((a b) ^ (c d)) | ((a b d) ^ (b c d)); endmodule;module example3_2n1 (a,b,c,d,f); input a,b,c,d; output f; reg[3:0] f; always@(a or b or c or d ) begin if(a==1 b==1) f[0]=1; else if (b==1 c==1) f[0]=1; else if(b==0 c==0) f[0]=1; else f[0]=0; end endmodule ;溜延伐娠恳兹磊且羡伯养样擦萎东势蚌寸苹帚义荐板两白烛境残磅嘛晃嘶东北大学EDA数字系统设计第三章改东北大学EDA数字系统设计第三章改;3.1.2 常用编码器设计; I0` I1` I2` I3` I4` I5` I6` I7`;输出函数;module example3_31 (i,y); input[7:0] i; output[2:0] y; ? assign y[0] = ~( ~ i[1] ~ i[3] ~i[5] ~ i[7]); assign y[1] = ~( ~ i[2] ~ i[3] ~i[6] ~ i[7]); assign y[2] = ~( ~ i[4] ~ i[5] ~i[6] ~ i[7]); endmodule ;module example3_32 (i,y); input[7:0] i;output[2:0] y; reg[2:0] y; always @(i) begin case (i) 8 y = 3b000; 8 y = 3b001; 8 y = 3b010; 8 y = 3b011; 8 y = 3b100; 8 y = 3b101;