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Application Note: Virtex-II and Virtex-II Pro Devices R 64B/66B Encoder/Decoder Author: Nick McKay and Matt DiPaolo XAPP687 (v1.0) November 21, 2003 Summary This application note describes the encoding and decoding blocks of the 64B/66B encoding scheme. This application allows designs to use the RocketIO™ transceiver of the Virtex-II Pro™ device or an external SerDes with either Virtex-II™ or Virtex-II Pro devices. Introduction Serial standards use an embedded clock in the data stream. To ensure the Clock Data Recovery (CDR) can track the embedded clock; a transition rich data stream is required. In the past, 8B/10B encoding provided the transition rich data along with a DC balanced data stream for many standards, including 1X and 2X Fibre Channel and Gigabit Ethernet. However, as serial rates increase to 3.125 Gbits/s and greater, the overhead of 8B/10B encoding becomes unacceptable in standards such as 10G Fibre Channel and 10G Gigabit Ethernet. To reduce the overhead, 64B/66B encoding was created. This scheme encodes 64 bits of data into 66 bits, providing a 3% overhead compared to the 20% overhead of 8B/10B encoding. Figure 1 shows how the 64B/66B encode/decode logic of this application fits in a complete system. This application note provides detailed information on the reference design indicated in grey. It does not cover the scrambler, descrambler, synchronization block, or gearbox. T