数字集成电路设计习题-chapter4_ex.pdfVIP

1 Chapter 4 Problem Set Chapter 4 Problems 1. [M, None, 4.x] Figure 0.1 shows a clock-distribution network. Each segment of the clock net- work (between the nodes) is 5 mm long, 3 µm wide, and is implemented in polysilicon. At each of the terminal nodes (such as R) resides a load capacitance of 100 fF. a. Determ