d,jk触发器,sr触发器.docVIP

使用if语句设计一个带同步清零（低电平有效）和异步置数（高电平有效） 端的d触发器。 library ieee; use ieee.std_logic_1164.all; entity dff1 is port (clk,d,clr,set:in std_logic; q:out std_logic); end; architecture fl of dff1 is begin process(clk,clr,set) begin if set=1 then q=1; elsif clkevent and clk=1 Then if clr=0 then q=0; else q=d; end if; end if; end process; end; 2 使用if语句和case语句设计一个带异步清0（高电平有效）和同步置数（低电平有效）端的jk触发器、 library ieee; use ieee.std_logic_1164.all; entity jk is port(clk,clr,set,j,k:in std_logic; q:out std_logic); end; architecture fl of jk is variable q_s:std_logic; signal a: std_logic_vector(1 downto 0); begin a=jk; process(j,k,clr,clk,set) variable q_s:std_logic; begin if clr=1 then q=0; elsif clkevent and clk=0 Then if set=0 then q=1; else case a is when 00=q_s:=q_s; when 01=q_s:=0; when 10=q_s:=1; when 11=q_s:=not q_s; end case; end if; end if; q=q_s; end process; end; 3设计sr触发器 library ieee; use ieee.std_logic_1164.all; entity sr1 is port(s,r,clk:in std_logic; q:out std_logic); end; architecture fl of sr1 is signal a:std_logic_vector(1 downto 0); begin a=sr; process(clk,a) variable b:std_logic; begin if clk=1 then case a is when 00=b:=b; when 01=b:=0; when 10=b:=1; when 11=b:=Z; end case; end if; q=b; end process; end;