硬件描述语言和数字系统开发(第8章)-10.pptVIP

硬件描述语言与数字系统开发;第8章 VHDL应用举例;library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity x3 is port( en:in std_logic; d:in std_logic_vector(9 downto 0); q:out std_logic); end x3; architeture behave of x3 is begin process(en,d) variable n: integer range 0 to 20; begin if enevent and en =1 then n:=0;;奇数分频器的VHDL设计;奇数分频器仿真波形;数控分频器的VHDL设计; CNT8 := D; --当CNT8计数计满时，输入数据D被同步预置给计数器CNT8 FULL = 1; --同时使溢出标志信号FULL输出为高电平 ELSE CNT8 := CNT8 + 1; --否则继续作加1计数 FULL = 0; --且输出溢出标志信号FULL为低电平 END IF; END IF; END PROCESS P1 ; P2: PROCESS(FULL) VARIABLE CNT2 : STD_LOGIC; BEGIN IF FULLEVENT AND FULL = 1 THEN CNT2 := NOT CNT2; --如果溢出标志信号FULL为高电平，D触发器输出取反 CLKOUT = CNT2; END IF; END PROCESS P2 ; END one;;数控分频器仿真波形;计数/译码驱动/扫描显示电路设计; LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY SCAN_LED IS PORT ( CLK : IN STD_LOGIC; --扫描时钟信号输入 A1，A2，A3，A4，A5，A6，A7，A8 : IN INTEGER RANGE 0 TO 15; SG: OUT STD_LOGIC_VECTOR(6 DOWNTO 0); --段控制信号输出(g-a) BT: OUT STD_LOGIC_VECTOR(8 DOWNTO 1)）;--位控制信号输出(k8-k1) END SCAN_LED; ARCHITECTURE one OF SCAN_LED IS SIGNAL CNT8:STD_LOGIC_VECTOR(2 DOWNTO 0); SIGNAL A :INTEGER RANGE 0 TO 15; BEGIN P1：PROCESS( CNT8 ) BEGIN ; CASE CNT8 IS WHEN 000 = BT =; A = A1 ; WHEN 001 = BT =; A = A2 ; WHEN 010 = BT =; A = A3 ; WHEN 011 = BT =; A = A4 ; WHEN 100 = BT =; A = A5 ; WHEN 101 = BT =; A = A6 ; WHEN 110 = BT =; A = A7 ; WHEN 111 = BT =; A = A8 ; WHEN OTHERS = NULL ; END CASE ; END PROCESS P1; P2：PROCESS(CLK) BEGIN IF CLKEVENT AND CLK = 1 TH