各种总线分析(Various bus analysis).doc

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各种总线分析(Various bus analysis)

各种总线分析(Various bus analysis) I. SPI bus description Serial peripheral interface SPI (serial peripheral interface) bus technology is a synchronous serial interface of Motorola Corporation and Motorola company production of the vast majority of MCU (micro controller) are equipped with SPI hardware interface, such as the 68 series MCU. SPI is used in CPU for full duplex and synchronous serial communication with various peripheral devices. SPI can send and receive serial data at the same time. It is only four lines of MCU can be completed with a variety of peripheral devices of the communication, the four lines are: serial clock line (CSK), input / output data from the host machine line (MISO), the output / input data from the host machine line (MOSI), active low select line CS from the machine. These peripheral devices can be simple TTL shift registers, complex LCD display drivers, A/D, D/A conversion subsystems, or other MCU. When SPI works in the shift register data bit from the output pin (MOSI) output (high first), at the same time from the input pin (MISO) data received by the displacement to the shift register (high front). After sending a byte, the byte data received from another peripheral device is moved into the shift register. The main SPI clock signal (SCK) enables synchronization of transmissions. The typical system diagram is shown below. The main features of SPI are: it can send and receive serial data at the same time; Can work as host or slave; Provides a programmable clock frequency; End of transmission interrupt flag; Write conflict protection; Bus contention protection etc.. Figure 2 shows the four ways in which the SPI bus works, with the most widely used methods of SPI0 and SPI3 (solid line representation): In order to exchange data with the peripheral, the SPI module can configure its output, serial synchronization, clock polarity and phase according to the requirements of peripheral operation, and the clock polarity (CPOL) has no significant imp

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