飞思卡尔备份信息 1.pptVIP

HCS12 Overview;Main Features:;MC9S12DP256;HCS12 Building Blocks;HCS12 Documentation;CPU Core(Programming Model); Core Features (1 of 2);Core Features (2 of 2);HCS12 Programmers Model;Condition Code Register;HCS12 Serial Interface Features;Pin Logic;o;IIC Features;msCAN Bus;BDLC CONTROLLER (J1850);Analog to Digital Converter;PWM FEATURES;HCS12 Device Identification;Crystal oscillator (OSC) Colpitts with translated GND (as per HC12D- Family) or traditional Pierce configurations Crystal Monitor (CM) same as on HC12D-Family Clock Quality Checker (CQC) ensures valid clock for operation Phase Locked Loop (PLL) same as on HC12D-Family Self Clock Mode with internal oscillator System Clocks Generator (CGEN) simplified clock chain: Core clock = PLLCLK or OSCCLK Peripherals clock = PLLCLK/2 or OSCCLK/2 (25% duty) ECLK = PLLCLK/2 or OSCCLK/2 (50% duty) no Slow Mode Clock System Reset Generator (RGEN) same Reset functionality as on HC12D-Family: Reset by POR, COP, ext. Reset, Clock Monitor Real Time Interrupt (RTI) - slightly different divider chain Watchdog (COP) - slightly different divider chain LOW POWER OSCILLATOR SUPPORTS OPERATION UP TO 33 MHz ;Power Saving Design Features: Low power Oscillator design (Engineered to avoid power-wasting harmonics) User Configurable Low Power Peripheral modes RUN Mode (full operation): 65 mA max - However peripherals automatically shut down if not in use WAIT Mode (CPU sleeping): Peripheral modules can be configured in power conservation mode 40 mA max with all modules enabled 5 mA max with only Real Time interrupt enabled STOP Mode (All modules stopped - Osc etc): 30uA * Typical Pseudo STOP Mode (All modules stopped): 350uA * Typ - However Osc runs in low power mode enabling wake-up as fast as in WAIT mode *At 27oC.;HCS12 Resets;Crystal Monitor Function: Detects crystal failure and takes user-specified action - bad clock detect. Clock Quality Checker: Performs a window check on the oscillator to ensure that the MCU on