Intel微机原理第10盏穆(存储器接口)-1.ppt

Memory Interface;1. Memory Devices;存储器引脚;数据线---- All memory devices have a set of data input/output. two main points: ? utility ? catalog listing ;选择线---- Each memory device has at least one chip select (CS) or chip enable (CE) pin that enables the memory device. two main points: ? active level ? more than one connection ;控制线----Each memory device has at least one control pin. For ROMs, an output enable (OE) or gate (G) is present. For RAMs, a read-write (R/W) or write enable (WE) and read enable (OE) are present. two main points: ? ROM control connection ? RAM control connection ;存储器引脚图;EPROM 2716 (2kX8);2716读时序;SRAM 4016 (2Kx8);DRAM 4464 (64K X 4);4464时序;SRAM 和 DRAM;SIMM 和 DIMM;10-2 地址译码;简单的与非门译码器;地址分布;3-8 译码器;译码电路;PROM地址译码器TPB28L42 (512X8);PLD可编程译码器;AMD 16L8 PAL;PAL 16L8译码器--8X2764（8KX8）;10-3 8088和80188存储器接口;8位 EPROM 接口;8位 SRAM 接口;Parity Checking 奇偶校验;74AS280;Evaluation only. Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0. Copyright 2004-2011 Aspose Pty Ltd.;地址确定： A19 A18 A17 A16 A15 1 0 0 0 0 选中U1，U5 1 0 0 0 1 选中U2，U5 U1地址范围=8000~87FFH U2地址范围=8800~8FFFH;奇偶校验确定： 写入数据时，U6作用 若为奇数，U6输出0；若为偶数，输出1 读出数据时，U7作用 原数据为奇数，U7输出0，正确 数据变为偶数（出错），U7输出1 原数据为偶数，DO=1，U7输出0，正确 数据变为奇数（出错），DO=1，U7输出1 每个数据按奇数个1存储，奇校验;10-4 8086,80186,80286,80386SX （16位）存储器接口;高（奇）、低（偶）双排结构;BHE 和 BLE;High bank WRiteLow bank WRite;80386SX存储器接口;10-5 80386DX和80486存储器接口;10-6 Pentium(64位)存储器接口;Evaluation only. Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0. Copyright 2004-2011 Aspose Pty Ltd.;Pentium存储器接口;10-7 动态RAM;DRAM;EDO;SDRAM;EDO DRAM(Extended Data Output DRAM--扩展数据输出) 始终将RAS选中的256位数据存放在锁存器中，不需要等待状态即可获得数据。比DRAM提高15%~20%性能。 SDRAM(Sychronous DRAM--同步DRM) 可以减少第2，3，4次从器件读出数据的时间。比EDO提高10%性能。;DRAM控???器;Intel 82C08;Evaluation only. Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0. Copyright 2004-2011 Aspose Pty Ltd.;Question