计算机组成原理实验乘法器.docx

学院计算机组成原理实验报告?年级　　学号　姓名　成绩　　专业　实验地点　指导教师　　　实验项目乘法器　　实验日期　实验目的：理解并掌握乘法器的原理实验步骤打开QuartusII。将子板上的JTAG端口与PC机的并行口用下载电缆连接。打开实验台电源。执行 Tools—Programmer命令，将shifter.sof下载到FPGA中。注意在执行Programmer命令中应在Programmer/configure下的方框中打勾，然后下载。在实验台上通过模式开关选择FPGA-CPU独立调试模式010.将短路子DZ3短接且短路子DZ4 断路。使FPGA-CPU所需要的时钟使用正单脉冲时钟。实验代码--实验6.6 Booth乘法器LIBRARY IEEE;USE IEEE.Std_logic_1164.ALL;ENTITY booth_multiplier ISGENERIC(k : POSITIVE := 3); --input number word length less onePORT( multiplicand : IN BIT_VECTOR(k DOWNTO 0);multiplier : IN BIT_VECTOR(k DOWNTO 0);clock : IN BIT; product : INOUT BIT_VECTOR((2*k + 2) DOWNTO 0);final : OUT BIT );END booth_multiplier;ARCHITECTURE structural OF booth_multiplier ISSIGNAL mdreg : BIT_VECTOR(k DOWNTO 0);SIGNAL adderout : BIT_VECTOR(k DOWNTO 0);SIGNAL carries : BIT_VECTOR(k DOWNTO 0);SIGNAL augend : BIT_VECTOR(k DOWNTO 0);SIGNAL tcbuffout : BIT_VECTOR(k DOWNTO 0);SIGNAL adder_ovfl : BIT;SIGNAL comp : BIT;SIGNAL clr_md : BIT; SIGNAL load_md : BIT;SIGNAL clr_pp : BIT;SIGNAL load_pp : BIT;SIGNAL shift_pp : BIT;SIGNAL boostate : NATURAL RANGE 0 TO 2*(k + 1) :=0;BEGINPROCESS --main clocked process containing all sequential elementsBEGIN WAIT UNTIL (clockEVENT AND clock = 1); --register to hold multiplicand during multiplication IF clr_md = 1 THENmdreg = (OTHERS = 0); ELSIF load_md = 1 THENmdreg = multiplicand; ELSEmdreg = mdreg; END IF; --register/shifter accumulates partial product values IF clr_pp = 1 THENproduct = (OTHERS = 0);product((k+1) downto 1) = multiplier; ELSIF load_pp = 1 THENproduct((2*k + 2) DOWNTO (k + 2)) = adderout; --add to top half product((k+1) DOWNTO 0) = product((k+1) DOWNTO 0); --refresh bootm half ELSIF shift_pp = 1 THENproduct = product SRA 1; --shift right with sign extend ELSEproduct = product; END IF;END PROCESS;--adder adds/subtracts partial pro