管线可能遇到的问题(datahazard).pptVIP

第七章 PIPELINING Outline What is pipelining? The basic pipeline for a RISC instruction set The major hurdle of pipelining – pipeline hazards Data hazards Control hazards Performance What is pipelining? Pipelining is an implementation technique whereby multiple instructions are overlapped in execution. Not visible to the programmer Each step in the pipeline completes a part of an instruction. Each step is completing different parts of different instructions in parallel Each of these steps is called a pipe stage or a pipe segment. What is pipelining? Like Assembly line in the factory The time required between moving an instruction one step down the pipeline is a machine cycle. All the stages must be ready to proceed at the same time Slowest pipe stage dominates Machine cycle is usually one clock cycle (sometimes two, rarely more) The pipeline designer’s goal is to balance the length of each pipeline stage. Pipeline Stages Every stage is completed within one cpu clock F (Fetch) D (Decode) E (Execute) W (Write) How about the clock of IF Because all the stages must be completed at the same time, we can not expect IF to access main memory Thus IF must access L1 cache When cache is built in CPU, the access time of cache is almost the same as the time to execute other operations within CPU Slowest pipe stage dominates Performance of Pipeline If the stages are perfectly balanced, then the time per instruction on the pipelined machine – assuming ideal conditions--is equal to Pipeline Hazards Structural hazards Caused by resource conflict Possible to avoid by adding resources – but may be too costly Data hazards Instruction depends on the results of a previous instruction in a way that is exposed by the overlapping of instructions in the pipeline Can be mitigated somewhat by a smart compiler Control hazards When the PC does not get just incremented Branches and jumps - not too bad Pipeline can not accelerate the execution time of instructions, actually it will prolong