Guide to Drawing Clean Schematics with Virtuoso英文教材.pdf

Guide to Drawing Clean Schematics with Virtuoso A Cadence EDA Tools Help Document Created by Casey Wallace, Spring 2006 Shown in the figure below is an attempt at drawing an XOR schematic using Virtuoso schematic editor. The drawing is so unorganized that it is difficult to tell what circuit has actually been modeled. In addition, it contains at least five major wiring mistakes that are difficult to identify without a lengthy and careful examination. There are a few simple techniques that can be used to draw schematics that will vastly improve their readability, as well as make any wiring problems much easier to debug. Guide to Drawing Clean Schematics with Virtuoso 1 Tip #1: Net naming using primary input pins Any net (i.e. wire) connected to a pin is automatically given the name of the pin. Additionally, any net given the same name as a pin becomes connected to that pin. Therefore, you can replace much of the wiring from pin connections, and eliminate the using of multiple pins with an identical name by utilizing net naming. You can add a label to a wire by pressing ‘l’, entering the name of the label, and then clicking on the wire. Guide to Drawing Clean Schematics with Virtuoso 2 Tip #2: Net naming intermediate nets In order to connect two nets together, you may label them with the same name. If the wire is not connected to a primary input, output, or supply net in the schematic (i.e. an intermediate net), you may give the wire any name you wish. In the figure below, the inverter output nets are named. All transistors’ gate terminals connected to these inverter outputs are connected to a short wire and given the same name. All nets sharing the same name indicate a share