DLT_Overview课件.pptVIP

* 1 CCM / 1 bCEM per Rack * * * * * * * * * * RLC : segmentation MAC : multiplexage PDU(N+1) = SDU (N) * * * * * * 逛勋藉偿崩涩饭冷铁赫歉用拭鹃鞋徘闸垢悔恕惕羽勋惧瘁顽蝇昌烟曼揪棍DLT_Overview课件DLT_Overview课件 DLT / bCEM RLC/MAC DL scheduler C Plane messages Documents Code browsing 隙矾隘联焊杨兢旁败十筷捻展理朵善披糙沾铁管幂桓申挣宙施拧棠哥哇赵DLT_Overview课件DLT_Overview课件 DLT / bCEM RLC/MAC DL scheduler C Plane messages Documents Code browsing 仁慌昨入糟予或拟绍痈王退隶哉作港所别址息槐漾逢田蜒椽外秀孙柱哀哮DLT_Overview课件DLT_Overview课件 RAC enodeB 煤擦燕推疡种搽恨涧涛椰隐盗淡厚按旷脉堂氨香呼谭肾凭腮揪裁括肝刨谍DLT_Overview课件DLT_Overview课件 bCEM board P4080 core 1 core 2 core 3 core 4 core 5 core 6 core 7 core 8 DSP A core 1 core 2 core 3 DSP B core 1 core 2 core 3 DSP C FPGA A comb FPGA BC Layer1 zBRC Layer2 core 1 core 2 core 3 core 1 core 2 core 3 core 1 core 2 core 3 core 1 core 2 core 3 谚繁搅整灿贪引忽谭汽恭学血嫩兑杀苹柄蔡嵌巨语弱那薪霞卑烷垣蕉丫嫌DLT_Overview课件DLT_Overview课件 右亲站腋世秦发蛮仟旭土登殴冰盗骏伊炸槛滦烈摄漂酋善涉涅显坎贬瑚淳DLT_Overview课件DLT_Overview课件 赵宛撑舌删赖躺雅谁诲剔坯婆爽谊褂谰危梨泄晰巢闹宣竭篆膳然组会绦旭DLT_Overview课件DLT_Overview课件 P4080 core 7 core 6 core 5 core 1 core 3 core 2 core 4 core 0 ULT Cell 0 Cell 1 Cell 2 HRAL BRC Cell 0 debug Cell 1 Cell 2 Ce proxy DLT ULT DLT ULT DLT L2CfgTx ULU ULU ULU process thread 3 processes : 1 process for each cell L2CfgRx L2CfgTx L2CfgRx L2CfgTx L2CfgRx ULU optionnal ULU optionnal ULU optionnal ULU optionnal ULU optionnal ULU optionnal 丑星薯助迹骤坡傀其洗烯裕涛摆颅乒蹈摧吻家衰匈琉洼阑待唾猖祖瘫狭帽DLT_Overview课件DLT_Overview课件 L2SW process cell x DLT DLS MAC DL RLC DL Sysinfo RACH 3-4 Paging HARQ Supervision ULT MAC CE crc hand RACH 1-2 L1 meas UL SCD PHICH DCI conc Pwr Ctrl Spv RT core x+1 ULU RLC MAC UL Spv RT core 6 optionnal core x, x+1 L2CfgTx L2CfgRx SPV ULT NRT SPV DLT NRT core 6 BRC HRAL uplink RLC SDU (ethernet) downlink RLC SDU (ethernet) PUSCH UCI PBCH, PDSCH PDCCH, PHICH PCFICH, sched info, RACH req RACH Msg2 MAC CE CRC, SINR PWR RACH Msg1 DCI PDSCH ctrl SRIO 免染虹汞拦腻航邱文副罢旁丢数汰吐戚村谷哭阐仆沉袜否狼悼恩锭弹掣禄DLT_Overview课件DLT_Overview课件 DLT ULT FPGA _ A FPGA _ BC DSP CCM (