.脉冲发生器.docVIP

节拍脉冲发生器 library ieee; use ieee.std_logic_1164.all; entity jiepai is port(stop,step,start,clk:in std_logic; p:out std_logic_vector(3 downto 0)); end; architecture a of jiepai is signal x,y:std_logic_vector(3 downto 0); begin process(stop,step,start,clk) begin if clkevent and clk=1 then if stop=0 then p=0000; x=0000;end if; if start=0 and stop=1 and step=1 then x=0001; elsif start=1 and stop=1 and step=1 then case x is when 0001 =x=0010; when 0010 =x=0100; when 0100 =x=1000; when 1000 =x=0001; when others= x=0000; end case; end if; if step=0 and st