东南大学soc课件4 SoC架构(6学时).ppt

组成框图 在APB总线上使用PCLK总线时钟，在PAD中使用CLK32提供的时钟，所以RTC模块属于多时钟域设计。其中Sync_Pto32与Sync_32toP模块是保证两个时钟域同步而设置的。APB接口模块完成数据从PAD到APB域的接口转换， CLK32域的Time，Sample，WatchDog模块用来计时或形成中断。 寄存器列表 结构框图 寄存器列表 寄存器列表 * * * * * * * * * * * * * * * * * * **** ANIMATED ***** * * The main part of the EmbeddedICE logic is the watchpoint units, of which there are two. These allow breakpoint and watchpoints to be set. The reason for having two watchpoint unite is mainly historical - in the days when silicon area was very expensive and power consumption was more important, this represented a good compromise between functionality and cost. The Debug Control Register allows debugger to force debug related core pins. The Debug Status Register allows the debugger to monitor core status. The Communications Channel registers allow the core and debugger to communicate without first having to take the core to debug state (i.e. debug communications in real time). This will be explained in more detail later. Die size for ARM7TDMI on generic 0.25um process is just over 1.0mm2. The ‘I’ part occupies about 13% of the total die size ( if somebody asks: and use about 7% of the total power, if activated with DBGEN ). * Watchpoints Allow detection of an data access to an interesting memory location Will always be taken after the data access has occurred. Not important to stress this but - In the case of the ARM9, the following instruction will also execute before the core enters debug state (because the watchpoint will not trigger until the Memory stage of the relevant instruction has completed, by which time the Execute stage of the following instruction has also completed.) In this example the watchpoint is issued on an data write to address 0xF000. In this case, the data value is completely masked (0xfff… loaded to data mask register) as we are only interested in the access and not its value. The WP unit ignores what’s on the data bus, and in effect only monitors the address and control busses. Note that e