基于cpld的fpga快速配置电路的设计（Design of FPGA fast configuration circuit based on CPLD）.docVIP

下载本文档

1
0
约1.44万字
约 10页
2017-08-16 发布于河南
举报
版权申诉

基于cpld的fpga快速配置电路的设计（Design of FPGA fast configuration circuit based on CPLD）.doc

1、本文档共10页，可阅读全部内容。
2、原创力文档（book118）网站文档一经付费（服务费），不意味着购买了该文档的版权，仅供个人/单位学习、研究之用，不得用于商业用途，未经授权，严禁复制、发行、汇编、翻译或者网络传播等，侵权必究。
3、本站所有内容均由合作方或网友上传，本站不对文档的完整性、权威性及其观点立场正确性做任何保证或承诺！文档内容仅供研究参考，付费前请自行鉴别。如您付费，意味着您自己接受本站规则且自行承担风险，本站不退款、不进行额外附加服务；查看《如何避免下载的几个坑》。如果您已付费下载过本站文档，您可以点击这里二次下载。
4、如文档侵犯商业秘密、侵犯著作权、侵犯人身权等，请点击“版权申诉”（推荐），也可以打举报电话：400-050-0827(电话支持时间：9:00-18:30)。
5、该文档为VIP文档，如果想要下载，成为VIP会员后，下载免费。
6、成为VIP后，下载本文档将扣除1次下载权益。下载后，不支持退款、换文档。如有疑问请联系我们。
7、成为VIP后，您将拥有八大权益，权益包括：VIP文档下载权益、阅读免打扰、文档格式转换、高级专利检索、专属身份标志、高级客服、多端互通、版权登记。
8、VIP文档为合作方或网友上传，每下载1次，网站将根据用户上传文档的质量评分、类型等，对文档贡献者给予高额补贴、流量扶持。如果你也想贡献VIP文档。上传文档

基于cpld的fpga快速配置电路的设计（Design of FPGA fast configuration circuit based on CPLD）

基于cpld的fpga快速配置电路的设计（Design of FPGA fast configuration circuit based on CPLD） This article is contributed by iluckylee11 Pdf documents may experience poor browsing on the WAP side. It is recommended that you first select TXT, or download the source file to the local view. Integrated circuit application Design of FPGA fast configuration circuit based on CPLD Zhang Honggang, Xing Huanji, Wang Deshi (Institute of ordnance technology, Naval University of engineering, Hubei, Wuhan 430033, China) Abstract: the rapid parallel configuration of FPGA with CPLD and Flash devices is introduced, and the specific hardware circuit design and the internal programming idea of the key modules are given. Keywords: FPGA, parallel configuration, FlashCPLD FPGA based on SRAM Technology (field programmable gate array) is with the characteristics of high integration, strong logical function; digital logic circuit design using electricity should be FPGA, but can reduce the size of the circuit, high reliable system operation not provided, and the advanced development tools can make the circuit design and system debugging week period is greatly shortened; FPGA can be repeated indefinitely to erase, the digital system can be reconfigured in line, the design is more flexible, more powerful, easy to change and upgrade work. Because the FPGA static random access memory (SRAM) data will be lost after power off, the power on every time after the re allocation of data, how fast and efficient system such as speed of configuration data is written to the target device, and ensure the high power and off again after power on can reliably and automatically restore the configuration, has become the key to it the whole system. This paper makes preliminary study on the design of CPLD FPGA parallel data configuration method and circuit based on internal programming ideas and gives the specific hardware circuit design and key module. Comparison of 1FPGA data configuration methods There are a lot of data FPGA c