1个可以综合的Verilog写的FIFO存储器.docVIP

一个可以综合的Verilog 写的FIFO存储器 Synthesizable FIFO Model This example describes a synthesizable implementation of a FIFO. The FIFO depth and FIFO width in bits can be modified by simply changing the value of two parameters, `FWIDTH and `FDEPTH. For this example, the FIFO depth is 4 and the FIFO width is 32 bits. The input/output ports of the FIFO are shown in Figure F-1. Figure F-1. FIFO Input/Output Ports Input ports All ports with a suffix N are low-asserted. Clk?Clock signal RstN?Reset signal Data_In?32-bit data into the FIFO FInN?Write into FIFO signal FClrN?Clear signal to FIFO FOutN?Read from FIFO signal wo parOutput ports F_Data?32-bit output data from FIFO F_FullN?Signal indicating that FIFO is full F_EmptyN?Signal indicating that FIFO is empty F_LastN?Signal indicating that FIFO has space for one data value F_SLastN?Signal indicating that FIFO has space for two data values F_FirstN?Signal indicating thbits.at there is only one data value in FIFO ?The Verilog HDL code for the FIFO implementation is shown in Example F-1. Example F-1 Synthesizable FIFO Model //////////////////////////////////////////////////////////////////// // FileName: Fifo.v // Author : Venkata Ramana Kalapatapu // Company : Sand Microelectronics Inc. // (now a part of Synopsys, Inc.), // Profile : Sand develops Simulation Models, Synthesizable Cores and // Performance Analysis Tools for Processors, buses and // memory products. Sands products include models for // industry-standard components and custom-developed models // for specific simulation environments. //////////////////////////////////////////////////////////////////// `define FWIDTH 32 // Width of the FIFO. `define FDEPTH 4 // Depth of the FIFO. `define FCWIDTH 2 // Counter Width of the FIFO 2 to power // FCWIDTH = FDEPTH. module FIFO( Clk, RstN, Data_In, FClr