aucuntitredediapositive-universitégrenoblealpes.ppt

Conclusion HLS allows to automatically generate several RTL architectures From an algorithmic/behavioral description and a set of constraints HLS allows to generate VHDL models for synthesis purpose SystemC simulation models for virtual prototyping HLS allows to explore the design space of Hardware accelerators MPSoC architectures including HW accelerators GAUT is free downloadable at http://lab-sticc.fr/www-gaut Université de Bretagne-SudLab-STICC Philippe COUSSYphilippe.coussy@univ-ubs.fr Architecture generation Specification RTL architecture Operators Library Selection HLS steps: scheduling Allocation Scheduling Binding Compilation Intermediate format Constraints + N0 × N1 - N3 Booth RCA RCA *1 *1 *1 + N2 Synthesis steps Compilation Generates a formal modeling of the specification Selection Chooses the architecture of the operators Allocation Defines the number of operators for each selected type Scheduling Defines the execution date of each operation Binding (or Assignment) Defines which operator will execute a given operation Defines which memory element will store a data Architecture generation Specification RTL architecture Operators Library Selection HLS steps: binding Allocation Scheduling Binding Compilation Intermediate format Constraints + × - + × - Operation binding n01 n21, n11 n22, n12 R1 R3 R4 n02 R2 n31 R5 n32 R6 Data Binding Booth RCA RCA *1 *1 *1 + Synthesis steps Compilation Selection Allocation Scheduling Binding (or Assignment) Architecture generation Writes out the RTL source code in the target language e.g. VHDL or SystemC HLS steps: output + × - × Operation binding n01 n21, n11 n22, n12 R1 R3 R4 n02 R2 n31 R5 n32 R6 Data binding Architecture generation Specification RTL architecture Operators Library Selection Allocation Scheduling Binding Compilation Intermediate format Constraints Controller - FSM controller - Programmable controller Datapath components - Storage components - Functional units - Connectio