aucuntitredediapositive-universitégrenoblealpes.ppt

Conclusion HLS allows to automatically generate several RTL architectures From an algorithmic/behavioral description and a set of constraints HLS allows to generate VHDL models for synthesis purpose SystemC simulation models for virtual prototyping HLS allows to explore the design space of Hardware accelerators MPSoC architectures including HW accelerators GAUT is free downloadable at http://lab-sticc.fr/www-gaut Université de Bretagne-SudLab-STICC Philippe COUSSYphilippe.coussy@univ-ubs.fr Architecture generation Specification RTL architecture Operators Library Selection HLS steps