原创力文档- 1、本文档共39页，可阅读全部内容。
- 2、原创力文档（book118）网站文档一经付费（服务费），不意味着购买了该文档的版权，仅供个人/单位学习、研究之用，不得用于商业用途，未经授权，严禁复制、发行、汇编、翻译或者网络传播等，侵权必究。
- 3、本站所有内容均由合作方或网友上传，本站不对文档的完整性、权威性及其观点立场正确性做任何保证或承诺！文档内容仅供研究参考，付费前请自行鉴别。如您付费，意味着您自己接受本站规则且自行承担风险，本站不退款、不进行额外附加服务；查看《如何避免下载的几个坑》。如果您已付费下载过本站文档，您可以点击 这里二次下载。
- 4、如文档侵犯商业秘密、侵犯著作权、侵犯人身权等，请点击“版权申诉”（推荐），也可以打举报电话：400-050-0827(电话支持时间：9:00-18:30)。
查看更多
[ECE VHDL 课件] ECE 448 FPGA and ASIC Design with VHDL - 13 advanced testbenches
ECE 448
Lecture 13;Sources;Simple Testbench;Advanced Testbench;Source
of
Representative
Inputs;Test vectors;Asserts Reports;Assert;Assert - syntax;Assert - Examples;Report - syntax;Report - Examples;library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity example_1_tb is
end example_1_tb;
architecture behavioral of example_1_tb is
signal clk : std_logic := 0;
begin
clk = not clk after 100 ns;
process
begin
wait for 1000 ns;
report Initialization complete;
report Current time = timeimage(now);
wait for 1000 ns;
report SIMULATION COMPLETED severity failure;
end process;
end behavioral;;Records;Records;Variables;Variable – Example (1);Variable – Example (2);Variables - features;Using Arrays of Test Vectors
In Testbenches;Testbench (1);Testbench (2);Testbench (3);Testbench (4);Testbench (5);File I/O;Design Under Test (1);Design Under Test (2);Test vector file (1);Test vector file (2);Testbench (1);Testbench (2);Testbench (3);Testbench (4);Testbench (5);Testbench (5);Testbench (6);Testbench (7);Hex format
文档评论（0）