algorithmic optimization of bdds and performance evaluation for multi-level logic circuits with area and power trade-offsbdd算法优化和绩效评估的多级逻辑电路区域和力量的权衡.pdfVIP

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algorithmic optimization of bdds and performance evaluation for multi-level logic circuits with area and power trade-offsbdd算法优化和绩效评估的多级逻辑电路区域和力量的权衡.pdf

algorithmic optimization of bdds and performance evaluation for multi-level logic circuits with area and power trade-offsbdd算法优化和绩效评估的多级逻辑电路区域和力量的权衡

Circuits and Systems, 2011, 2, 217-224 doi:10.4236/cs.2011.23031 Published Online July 2011 (http://www.SciRP.org/journal/cs) Algorithmic Optimization of BDDs and Performance Evaluation for Multi-level Logic Circuits with Area and Power Trade-offs 1 2 Saurabh Chaudhury , Anirban Dutta 1 Department of Electrical Engineering , National Institute of Technology,

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algorithmic optimization of bdds and performance evaluation for multi-level logic circuits with area and power trade-offsbdd算法优化和绩效评估的多级逻辑电路区域和力量的权衡.pdfVIP