a fine grain configurable logic block for self-checking fpgas自检fpga的细粒度可配置逻辑块.pdfVIP

VLSI DESIGN (C) 2001 OPA (Overseas Publishers Association) N.V. 2001, Vol. 12, No. 4, pp. 527-536 Published by license under Reprints available directly from the publisher the Gordon and Breach Science Publishers imprint, Photocopying permitted by license only member of the Taylor Francis Group. A Fine Grain Configurable Logic Block for Self-checking FPGAs P. K. LALAa’* and A. WALKERb’t aDepartment of Computer Science and Computer Engineering, University ofArkansas, Fayetteville, AR 72701, USA; bDepartment ofElectrical Engineering, North Carolina AT State University, Greensboro, NC 27411, USA (Received 15 August 1999, ln finalform 11 September 2000) This paper proposes a logic cell that can be used as a building block for Self-checking FPGAs. The proposed logic cell consists of two 2-to-1 multiplexers, three 4-to-1 multiplexers and a D flip-flop. The cell has been designed using Differential Cascode Voltage Switch Logic. It is self-checking for all single transistor stuck-on and stuck-off faults as well as stuck-at faults at the inputs ofeach multiplexers and the Dflip-flop. The multiplexers and the D flip-flop provide either correct (complementary) output in the absence of above-mentioned faults; otherwise the outputs are identical. Keywords: Logic cell; DCVSL; Totally self-checking circuits; FPGAs; On-line testable; Fault- tolerant circuits 1. INTRODUCTION