an empirical algorithm for power analysis in deep submicron electronic designs实证分析算法对权力在深亚微米电子设计.pdfVIP

VLSI Design, 2002 Vol. 14 (2), pp. 219–227 An Empirical Algorithm for Power Analysis in Deep Submicron Electronic Designs MAY HUANGa,*, RAYMOND KWOKb and SHU-PARK CHANb aVirtual Silicon Technology, Inc., 1200 Crossman Ave., Sunnyvale, CA 94089, USA; bInternational Technological University, 1650 Warburton Ave., Santa Clara, CA 95050, USA (Received 10 September 1999; Revised 4 February 2000) An empirical algorithm applied to logic level power analysis in deep submicron VLSI designs is introduced in the paper. The method explores a static analysis strategy using unit functions to represent signal transitions. It can be extended to the use of a Register Transfer Level (RTL) power analysis after RTL codes are translated to Boolean equations. A new method for representing state-dependent power models is also introduced in the paper to reduce the complexity of power modeling and to improve the performance of power analysis. The modeling method supports not only the empirical power analysis, but also general simulation-based power analysis methods. Keywords: Analysis; Power consumption model; Power estimation; CMOS ASIC design; State- dependent power representation; Characterization INTRODUCTION Power consumption is proportional to switching activities. A simulation-based analysis includes pattern-dependent Power analysis becomes a very important consideration in approaches such as exhaustive simulation or applicable d