集成电路设计-07-时序逻辑设计.ppt

EIS-Wuhan University 集成电路设计 第七章 时序逻辑电路设计 Designing Sequential Logic Circuits 纲要 基本概念 组合逻辑与时序逻辑电路 有限状态机（FSM） Latch versus Register 锁存器 寄存器 动态锁存器/寄存器 时钟控制寄存器C2MOS 流水线 非双稳态时序电路 时序问题 ——Sequential Logic Sequential Logic Asynchronous Circuits Synchronous Circuits Finite State Machine （FSM) External inputs and states as the inputs Outputs，and Next state Clock，edge sensitive（positive or negative） Mealy versus Moore state machines Static vs Dynamic Storage Static storage preserve state as long as the power is on have positive feedback (regeneration) with an internal connection between the output and the input useful when updates are infrequent (clock gating) Dynamic storage store state on parasitic capacitors only hold state for short periods of time (milliseconds) require periodic refresh usually simpler, so higher speed and lower power Latches vs Flipflops Latches level sensitive circuit that passes inputs to Q when the clock is high (or low) - transparent mode input sampled on the falling edge of the clock is held stable when clock is low (or high) - hold mode Flipflops (edge-triggered)一般指触发器 edge sensitive circuits that sample the inputs on a clock transition positive edge-triggered: 0 ? 1 negative edge-triggered: 1 ? 0 built using latches (e.g., master-slave flipflops) Latch versus Register 7-2 锁存器（Latches） 类型 Latch-Based Design 时间定义与约束 改变输出 多路开关型锁存器 类型 Latch-Based Design— for sequential 时间定义（Timing Definitions ） Characterizing Timing 约束（System Timing Constraints） 约束2 寄存器维持时间：thold tcd-register + tcd-logic ? thold tcd-register 寄存器最小传播延迟 cd---Contamination Delay tcd-logic逻辑电路最小传播延迟 保证时序元件的输入数据在CLK边沿之后能够维持足够的时间，不会因为新进入的数据流而过早改变。 Positive Feedback: Bi-Stability VTC Meta-Stability Bistable Circuits （flip-flops） Writing into a Static Latch 多路开关型锁存器（Mux-Based Latches） Mux-Based Latch Mux-Based Latch 7-3 寄存器 主从式边沿触发寄存器 降低时钟负载 非理想时钟—时钟重叠 静态RS触发器—强信号写数据 Master-Slave (Edge-Triggered) Register Master-Slave Register 多路开关型寄存器的时序特性 寄存器时序参数 Setup Time, Hold Time