design methodology of a 32-bit arithmetic logic unit with an adaptive leaf-cell based layout technique32位算术逻辑单元的设计方法和基于自适应叶细胞的布局方法.pdfVIP

VLSI Design, 2002 Vol. 14 (3), pp. 249–258 Design Methodology of a 32-bit Arithmetic Logic Unit with an Adaptive Leaf-cell Based Layout Technique KISEON CHO and MINKYU SONG* Department of Semiconductor Science, Dongguk University, 3-26 Phil-Dong, Choong-Ku, Seoul 100-715, South Korea (Received 3 August 2000; Revised 6 September 2000) In general, an arithmetic logic unit (ALU) of a DSP core is composed of an adder, multiplier and shifte