FPGA的CIC滤波器的设计.docVIP

基于FPGA的CIC数字滤波器的设计 摘要：级联积分梳状（Cascade Integrator Comb，CIC）滤波器是数字系统中实现大采样率变化的多速率滤波器，已经证明是在高速抽取和插值系统中非常有效的单元，在数字下变频（DDC）和数字上变频（DUC）系统中有广泛的应用。它不包含乘法器，只是由加法器，减法器和寄存器组成，而且需要的加法器的数目也减少了许多，因此CIC滤波器比FIR和IIR滤波器更节省资源，并且实现简单而高速。本文主要讨论了CIC滤波器的基本原理和基于FPGA的仿真实现方法，具体是采用Verilog HDL语言编程，将滤波器分为积分器模块和梳状器模块2个部分，对每个模块进行具体的功能分析和设计实现，最后通过仿真对滤波器的性能进行分析，验证了设计的正确性。 关键词：CIC滤波器抽取FPGA；Verilog HDL the Design of Cascade Integrator Comb Filter Based on FPGA Abstract: CIC (Cascade Integrator Comb, CIC) filter is a digital system to achieve large changes in multi-rate sampling rate filter, which has been proven to be a very effective unit in the high-speed extraction and interpolation system. It is widely used in the digital down conversion (DDC ) and digital up conversion (DUC) systems. It does not contain the multiplier, but just composes by adders, subtractors and registers, and the number of needing adders is reduced a lot. So it takes fewer resources than FIR filter and IIR filter. And the speed of CIC filter is very high and it is also very convenient to realize. This article discusses the basic principles of CIC filter and the simulation way based on FPGA. The modules were described with Verilog HDL. Firstly, the filter was divided into two parts which were integration module and the comb module. Then the function of each module were analyzed and designed. Finally the performance of the filter was analyzed under ModelSim and the correctness of the design was verified. Keywords：CIC filterDecimation; FPGA; Verilog HDL 1. 引言： 数字滤波是数字信号分析中最重要的组成部分之一，数字滤波与模拟滤波相比，具有精度和稳定性高，系统函数容易改变，灵活性高，不存在阻抗匹配问题，便于大规模集成，可实现多维滤波等优点。 级联积分梳状（Cascade integrator comb，CIC）滤波器，是由Hogenauer引入的一种非常有效的高分解速率的数字滤波器结构，已经证明是在高速抽取和插值系统中非常有效的单元。它具有较好的抗混叠和抗镜像性能；它不包含乘法器，只是由加法器，减法器和寄存器组成，而且需要的加法器的数目也减少了许多，因此CIC滤波器比FIR和IIR滤波器更节省资源，并且实现简单而高速；无需存储滤波器的系数，结构规则易于拓展，无需外部控制，抽取倍数可变，对提高实时性和简化硬件有重要意义。 CIC滤波器的应用范围非常的广泛：由于其具有较好的抗混叠和抗镜像性能，可以实现任意采样率的转换，因此被用在软件无电接收机中；用于正交多速率调制系统中，但又不仅仅是局限在调制器中，只要CIC滤波器之前或之后有FIR滤波器，对CIC滤波器的通带衰减进行补偿以后，都能够以很小的代价换取最大的硬件