EDA实验16.docVIP

实验一：五人表决器 方案1-编程： library ieee; use ieee.std_logic_1164.all; entity vote5 is port(a,b,c,d,e:in std_logic; f:out std_logic); end; architecture vo of vote5 is begin f=(a and b and c) or (a and b and d) or (a and b and e) or (a and c and d) or (a and c and e) or (a and d and e) or (b and c and d) or (b and c and e) or (b and d and e) or (c and d and e); end; 方案2-作图： 实验二一位全加器 一、布尔方程实现全加器： LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY fulladder IS PORT (a,b,ci:IN STD_LOGIC; S, co:OUT STD_LOGIC); END fulladder; --以下是一位全加器结构体数据流描述 ARCHITECTURE Dataflow OF fulladder IS BEGIN S = a XOR b XOR ci; co = (a AND b) OR (b AND ci) OR (a AND ci); END Dataflow; 二、with select when实现全加器 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY fulladder IS PORT (a, b, ci: IN STD_LOGIC; s, co: OUT STD_LOGIC); END fulladder; ARCHITECTURE behavioral OF fulladder IS SIGNAL inputsingal:STD_LOGIC_VECTOR(2 DOWNTO 0); SIGNAL outputsingal:STD_LOGIC_VECTOR(1 DOWNTO 0); BEGIN inputsingal=abci; WITH inputsingal SELECT outputsingal = 00 WHEN 000, 10 WHEN 001, 10 WHEN 010, 01 WHEN 011, 10 WHEN 100, 01 WHEN 101, 01 WHEN 110, 11 WHEN 111, 00 WHEN OTHERS; s=outputsingal(1); co=outputsingal(0); END behavioral; 三、when else实现全加器 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ?ENTITY fulladder IS PORT (a, b, ci: IN STD_LOGIC; s, co: OUT STD_LOGIC); END fulladder; ARCHITECTURE behavioral OF fulladder IS BEGIN s = 1 WHEN (a= 0 AND b= 1 AND ci= 0) ELSE 1 WHEN (a= 1 AND b= 0 AND ci= 0) ELSE 1 WHEN (a= 0 AND b= 0 AND ci= 1) ELSE 1 WHEN (a= 1 AND b= 1 AND ci= 1) ELSE 0; co = 1 WHEN (a= 1 AND b= 1 AND ci= 0) ELSE 1 WHEN (a= 0 AND b= 1 AND ci= 1) ELSE 1 WHEN (a= 1 AND b= 0 AND ci= 1) ELSE 1 WHEN (a= 1 AND b= 1 AND ci= 1) ELSE 0; END behavioral; 四、if then else实现全加器 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY ful