High Frequency Trading Acceleration using FPGAs（高频交易使用fpga加速度）.pdf

High Frequency Trading Acceleration using FPGAs Christian Leber, Benjamin Geib, Heiner Litz University of Heidelberg 68131 Mannheim, Germany {christian.leber, benjamin.geib, heiner.litz}@ziti.uni-heidelberg.de Abstract—This paper presents the design of an application reduce trading costs and improve the informational efficiency specific hardware for accelerating High Frequency Trading of asset price [4]. Traders that employ arbitration strategies [5], applications. It is optimized to achieve the lowest possible latency on the other hand, try to correlate pricing information between for interpreting market data feeds and hence enable minimal related stocks or derivates and their underlying prices. round-trip times for executing electronic stock trades. The Liquidity detection comprises strategies that seek to discover implementation described in this work enables hardware large orders by sending out small orders which can be decoding of Ethernet, IP and UDP as well as of the FAST leveraged by the traders. All strategies have in common that protocol which is a common protocol to transmit market feeds. they require absolute lowest round-trip latencies as only the For this purpose, we developed a microcode engine with a fastest HFT firm will be able to benefit from an existing corresponding instruction set as well as a compiler which enables