Instruction Set Architecture University of Iowa（指令集架构爱荷华大学）.pdfVIP

Instruction Set Architecture Consider x := y+z. (x, y, z are memory variables) 1-address instructions 2-address instructions LOAD y (r :=y) ADD y,z (y := y+z) ADD z (r:=r+z) MOVE x,y (x := y) STORE x (x:=r) 3-address instructions ADDx, y, z (x:= y+z) 0-address instructions (for stack machines) push pop PUSH y (on a stack) PUSH z (on a stack) ADD POP x Points to Consider • Special-purpose or general purpose? • Word size and instruction size? [Now most instructions have 32-bits, and machines allow operation on 64-bit data operands] • Data types? [Whatever the application demands] • 0/1/2/3 address instructions, or a mix of them? [Most modern designs allow 3-address instructions, and pack them in a 32-bit frame] • How many addressing modes, and which ones? [Whatever the application demands] • Register or memory operands? [Register operands can be accessed faster, but you cannot have too many registers] • Instruction formats and instruction encoding. [Modern designs have fewer formats and they are less clumsy] Instruction Types BASIC INSTRUCTIONS Data Movement LOAD, STORE, MOVE Arithmetic Logical ADD, SUB, AND, XOR, SHIFT Branch JUMP (unconditional) JZ, JNZ (conditional) Procedure Call CALL, RETURN Input Output Memory-mapped I/O* Miscellaneous NOP, EI (enable interrupt) SPECIAL INSTRUCTIONS Multimedia instructions (MMX) Many SIMD or vector instructions operate simultaneously on 8 bytes | 4 half-words | 2 words Digital Signal Processors include multiply-and-accumulate (MAC) to efficiently compute the dot-produ