无符号乘法器（4-bit4-bit）.docVIP

无符号乘法器 (4-bit × 4-bit) ------------------------------------------------------- --Design unit:4-Bit*4-Bit multiple -- : --File name :unsigned_multi.vhd -- : --Description:Structual model of two input multipler.Input of type std_logic_vector -- : --Limitation :none -- : --System :VHDL93 -- : --Author :CaoGuangyuan,LinRongbiao -- :Department of Software and Conmunication -- :University of SUN YAT-SEN -- :GUANG ZHOU -- :hailang123cn@163.com -- --Revision :Version 1.0 ------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; entity full_adder is port ( A: in STD_LOGIC; B: in STD_LOGIC; C_in: in STD_LOGIC; S: out STD_LOGIC; C_out: out STD_LOGIC ); end full_adder; architecture dataflow of full_adder is begin S = A xor B xor C_in; --全加器 C_out = (A and B) or (C_in and (A xor B)); end dataflow; ---------------------------- library IEEE; use IEEE.std_logic_1164.all; entity unsigned_multi is port ( X: in STD_LOGIC_VECTOR (3 downto 0); Y: in STD_LOGIC_VECTOR (3 downto 0); Z: out STD_LOGIC_VECTOR (7 downto 0) ); end unsigned_multi; architecture structual of unsigned_multi is signal r0: STD_LOGIC_VECTOR (3 downto 0); signal r1: STD_LOGIC_VECTOR (3 downto 0); signal r2: STD_LOGIC_VECTOR (3 downto 0); signal r3: STD_LOGIC_VECTOR (3 downto 0); signal ca_temp1: STD_LOGIC_VECTOR (2 downto 0); signal ca_temp2: STD_LOGIC_VECTOR (2 downto 0); signal ca_temp3: STD_LOGIC_VECTOR (3 downto 0); signal ca_temp : STD_LOGIC_VECTOR (7 downto 0); signal C0, C1, C2,C3 : STD_LOGIC; signal C4, C5, C6,C7 : STD_LOGIC; signal C8, C9, C10,C11 : STD_LOGIC; signal ZERO: STD_LOGIC; component full_adder port ( A: in STD_LOGIC; B: in STD_LOGIC; C_in: in STD_LOGIC; S: out STD_LOGIC; C_out: out STD_LOGIC ); end component; begin --全加器运算 F0 : full_adder port map (A = r0(1), B = r1(0), C_in = ZERO, S = ca_temp(1), C_out = C0); F1 : full_adder port map (A