xds510-usb2.0 焊接调试说明（Xds510-usb2.0 welding commissioning instructions）.docVIP

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xds510-usb2.0 焊接调试说明（Xds510-usb2.0 welding commissioning instructions）.doc

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xds510-usb2.0 焊接调试说明（Xds510-usb2.0 welding commissioning instructions）

xds510-usb2.0 焊接调试说明（Xds510-usb2.0 welding commissioning instructions） 1, TI DSP USB2.0 simulator At present, the company DSP chip TI is used more and more widely, the DSP simulator is one of the necessary tools for DSP developers. Early DSP parallel simulator because transmission speed is slow, difficult to adapt to the needs of developers, and recently launched TI PCI560 emulator, because the price is high, and the use of PCI interface, the connection is convenient. Therefore, this paper introduces a USB2.0 based interface DSP simulator (TDS510/XDS510), the theory of data transmission speed can reach 448 Mb / s, and the USB interface can be charged plug, easy to use. The DSP simulator with CY7C68013 USB2.0 controller of American Cypress company as the core, to achieve the data in DSP to read and write and transfer functions. DSP developers can follow this method to develop a simulator, learn process simulator, so as to avoid the purchase price of the DSP simulator. 2 system hardware structure The whole system is based on USB2.0 controller CY7C68013 and JTAG scanning ACT8990 chip as the core, including E2PROM, voltage conversion chip, the bus driver and the voltage comparator. The 2.1 USB2.0 controller CY7C68013 CY7C68013 is a USB2.0 chip produced by Cypress, is a fully integrated solution. Main contents are as follows: 1 CY7C68013 enhanced 8051 microprocessor, 1 intelligent serial interface engine (SIE), 1 USB, 16 KB transceiver chip RAM (including 4 KB FIFO) memory and 1 general programmable interface GPIF (General Programmable Interface). The original structure can make the data transmission rate of 448 Mb / s, which allows the maximum bandwidth of USB2.0. Smart SIE hardware processing USB1.1 and USB2.0 protocol, so as to reduce the development time, and ensure USB compatibility. GPIF and master / slave endpoint FIFO (8 bit or 16 bit data bus) provides a simple and seamless connection interface for ATA, UT0PIA, EPP, PCM, CIA and DSP, and the peripheral connectio